1. Field of the Invention
The present invention relates to an arrangement and method of controlling memory access requests in digital data processing system. The memory access requests are issued from a central processing unit (CPU) (for example) operating under clocks which are different from those under which a main memory operates. The present invention enables an effective reduction in the waiting time of main memory access requests in the event of successive occurrences thereof.
2. Description of the Prior Art
In order to effectively increase the over-all performance of a digital processing system which includes high-speed units such as a CPU and input/output device controllers which operate under clocks faster than those under which a main memory operates, it is a known practice to provide a memory access request controller between the high-speed units and the main memory.
Throughout the instant specification, the faster and slower clocks in the system are respectively denoted by first and second clocks. The first clocks synchronize the high-speed units while the second clocks synchronize the operation of the main memory. Further, instructions and information which are not directly concerned with the present invention will not be referred to for brevity.
The memory access controller comprises two portions: the first portion is coupled to the high-speed units and operates under the first clocks, while the second portion is coupled to the main memory and operates under the second clocks. When a high-speed unit issues a main memory access request, the memory access controller stores memory access request information, which is accompanied by the access request, in a buffer and initiates an access to the main memory.
However, in the event that the memory access requests are successively generated and exceed the capacity of the buffer, the memory access controller refuses the receipt of a new request until the access controller receives an access reply from the main memory. This induces an undesirably long wait and is disadvantageous from an over-all system performance point of view.
The above-mentioned prior art will further be discussed with reference to FIGS. 1 and 2.
The arrangement shown in block diagram form in FIG. 1, comprises a memory access controller 10 which is interconnected between a main memory 12 and units which issue memory access requests. The units, which request memory access, include a CPU 14 and a plurality of input/output (I/O) device controllers 16a and 16b. The memory access controller 10 comprises first and second portions 18 and 20. The first portion 18 includes a plurality of units all of which operate under the first clocks, while the second portion 20 includes units operating under the second clocks.
In more detail, the first portion 18 comprises a memory access request information buffer controller 22, a memory access request information buffer 24, a counter 26, a reply controller 28 and a clock synchronizer 30. On the other hand, the second portion 20 comprises a memory access request receive register 32, a memory access request information read-out circuit 34, a clock synchronizer 36 and a reply receive register 38.
The I/O device controllers 16a and 16b are respectively, operatively coupled with I/O devices 40a-40n and 41a-41n which function under third clocks which are much slower than either of the first and second clocks.
It is assumed that the buffer 24 can store up to 16 words each of which is able to store one item of memory access request information. Each of the blocks 14, 16a and 16b, issues a memory access request which accompanies memory access request information. The access request information includes a main memory address to be accessed, a read/write instruction, and reply data or information which are held in the buffer 24 and not used to access the memory 12. Merely by way of example, the reply information is data which specifies an I/O device (40a, . . . , 40n, 41a, . . . , 41n) which has sent a memory access request to the corresponding I/O device controller (16a or 16b in this case). Although the CPU 14 also supplies reply information, the details thereof will be omitted for brevity. The reply information should be fed back to the request sender. It should be noted that the I/O devices are not dealt with as request senders. The I/O device controllers 16a and 16b are treated as such in the instant specification.
In the event that the I/O control circuit 16a (for example) issues a memory access request which accompanies access request information, the buffer controller 22 is responsive to the access request and stores the access request information in the buffer 24. It should be noted that the buffer controller 22 is able to specify the unit (16a, 16b or 18 in this case) which issues the memory access request. The information specifying a request sender is also stored in the buffer 24. The access request information stored in the buffer 24 are: (a) a memory address to be accessed, (b) a read/write instruction, (c) reply information, and (d) information determining which unit has issued the memory access request.
The buffer controller 22, upon receipt of a memory access request, applies it to the access request receive register 32 via the clock synchronizer 36, and counts up the counter 26. The content of the counter 26 corresponds to the number of access request information stored in the buffer 24. When the register 32 receives the memory access request, it feeds an instruction signal to the access request information read-out circuit 34. This circuit 34, in response to the signal applied thereto, applies a read-out signal to the buffer controller 22, whereby the corresponding memory access request information is read out from the buffer 24 and is applied to the request receive register 32 via the clock synchronizer 36. Thereafter, the memory access request information is applied from the register 32 to the main memory 12 which performs a read/write operation according to the access request information. As mentioned above, the reply information is not sent to the request receive register 32.
It should be noted that the main memory 12 stores and outputs data through a data bus 13. These data read/write operations are not concerned with the present invention and hence further descriptions thereof will be omitted for brevity.
The main memory 12 supplies the reply receive register 38 with memory reply data which includes two signals, one of which (first signal) indicates the unit which has issued the memory access request while the other (second signal) indicates whether or not memory access request has been performed. The memory reply data is then applied, via the clock synchronizer 30, to the reply controller 28. The controller 28, upon receipt of the memory reply data, applies the second signal to the buffer 24 in accordance with the first signal which specifies the location of the access request information within the buffer 24. Then, the buffer 24 applies the second signal plus the reply information to the unit (14, 16a or 16b) which has requested the memory access. The reply information has been stored in the buffer 24 as referred to previously.
On the other hand, the reply controller 28 counts down the counter 26, which in turn informs the buffer controller 22 that one memory access request has been completed. In the event that the buffer 24 stores up to the memory capacity thereof (viz., 16 request information in this case), the buffer controller 22 is able to accept a new memory access request in response to a signal applied from the counter 26. Since the buffer controller 22 deals with the memory access requests in the order of receipt, it is able to specify which memory portion of the buffer 24 is ready to store the next new request information.
The difficulty encountered in the above-mentioned prior art will further be discussed with reference to FIGS. 1 and 2.
It is assumed that the buffer controller 22 successively receives 16 memory access requests (a-1, b-1, c-1, . . . , p-1) from one or more of the CPU 14 and the circuits 16a, 16b. As mentioned previously, the buffer 24 is able to store 16 items of access request information and hence the controller 22 refuses receipt of the 17th request q-1. Upon the buffer controller 22 receiving the first request a-1, the controller 22 applies an access request a-2 to the request receive register 32. Further, the controller 22 induces the buffer 24 to store the memory access information which is accompanied by the access request a-1. Similar operations are performed on each of the other access requests.
The request information read-out circuit 34, in response to the request a-2 applied to the request receive register 32 starts to retrieve the corresponding access request information which has been stored in the buffer 24. Thus, the access request information, corresponding to the request a-1, is applied to and stored in the request receive register 32 and then fed to the main memory 12 as a signal a-3. After the memory 12 has completed the operation required by the request a-1, the memory 12 applies a memory reply information a-4 to the reply receive register 38, which in turn applies the memory reply data (equal to a-4 but denoted by a-5) to the reply controller 28. Thereafter, the buffer 24 applies the reply information stored in the buffer 24 plus the above-mentioned second signal (denoted by a-6 in FIG. 2) to the unit which has issued the request a-1 and which is advised that the buffer controller 22 is now ready for receipt of a new request q-1. The buffer controller 22, however, is in fact able to accept the 17th request immediately after the generation of the signal a-6 at time T3.
In FIG. 2, Ta represents a time period between time points T1 and T2 while Tb denotes a time period between time points T1 to T3. It is understood that during a time period between T2 and T3 (.apprxeq.Tb-Ta) the buffer controller 22 is unable to accept a new request.
If the memory capacity of the buffer 24 is increased, this problem may be solved. However, this approach will encounter another difficulty in that the volume of hardware is undesirably increased.